Mercury KOB WL560 User Manual download pdf (Page 35)

DRAM Clock/Drive Control

Scroll to this item and press <Enter> to view the following screen:

DRAM Clock/Drive Control

Item Help

Current FSB Frequency

Current DRAM Frequency

DRAM Clock [By SPD]

DRAM Timing [By Manual]

x SDRAM Cycle Length 3

x Bank Interleave Disabled

DRAM Command Rate [2T Command]

Menu Level

↑ ↓ → ← : Move Enter : Select +/-/PU/PD:Value: F10: Save ESC: Exit F1:General Help

F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults

Current FSB Frequency

This item displays the frontside bus (FSB) frequency. This is a display-only

item. You cannot make changes to this field.

Current DRAM Frequency

This item displays the memory (DRAM) frequency. This is a display-only item.

You cannot make changes to this field.

DRAM Clock (By SPD)

This item enables you to manually set the DRAM Clock. We recommend that

you leave this item at the default value.

DRAM Timing (By Manual)

Set this to the default value to enable the system to automatically set the

SDRAM timing by SPD (Serial Presence Detect). SPD is an EEPROM chip on

the DIMM module that stores information about the memory chips it contains,

including size, speed, voltage, row and column addresses, and manufacturer.

If you disable this item, you can use the following three items to manually set

the timing parameters for the system memory

SDRAM Cycle Length (3)

When synchronous DRAM is installed, the number of clock cycles of CAS

latency depends on the DRAM timing. We recommend that you leave this item

at the default value.

Bank Interleave (Disabled)

Enable this item to increase memory speed. When enabled, separate memory

banks are set for odd and even addresses and the next byte of memory can

be accessed while the current byte is being refreshed.

DRAM Command Rate (2T Command)

This item enables you to specify the waiting time for the CPU to issue the next

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Mercury KOB WL560 User Manual Page 35